1. Field of the Invention
The invention relates to a method and apparatus of reducing plasma-induced damage in a substrate.
2. Background of the Invention
In the manufacture of integrated circuits, plasma processes are often used for deposition or etching of various material layers. Plasma processing offers many advantages over thermal processing. For example, plasma enhanced chemical vapor deposition (PECVD) allows deposition to be achieved at a lower temperature than that required in an analogous thermal process. This is advantageous for processes with stringent thermal budget demands, e.g., in very large scale or ultra-large scale integrated circuit (VLSI or ULSI) device fabrication.
It has been known in the art that device damage may occur as a result of plasma processing, including deposition and etch processes. Typically, the susceptibility or degree of device damage depends on the stage of device fabrication and the specific device design. For example, a substrate with a relatively large antenna ratio (e.g., area of metal interconnect to area of gate) is more susceptible to gate oxide damage compared to one with a smaller antenna ratio, because of an increased charging effect. A substrate that has an insulating layer deposited thereon is also more susceptible to damage due to the accumulation of surface charges, and a buildup of potential gradients. Other plasma related effects, such as plasma non-uniformity, may give rise to electric field gradients that lead to device damage. Therefore, there is an ongoing need for methods and apparatus to reduce plasma-induced damage in a substrate.
Embodiments of the invention generally provide a method and apparatus for reducing plasma-induced damage by implementing a post-deposition ramp down of a plasma source power used for plasma generation. The ramp down of the plasma source power may be achieved by reducing the power to one or more intermediate levels in multiple steps, or in a continuous manner.